Capacitors are used extensively in electronic devices for storing an electric charge. The capacitors essentially comprise two conductive plates separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, is measured in farads and depends upon the area of the plates, the distance between them, and the dielectric value of the insulator. Capacitors are used in filters, in analog-to-digital converters (ADCs) in memories, and various control applications.
Capacitors in integrated circuits are usually fabricated from polysilicon, metal to polysilicon or metal to polycide structures. In most applications, such as in analogue to digital converters (ADC's), a capacitor whose capacitance does not vary with voltage is needed. A measure of the variation of capacitance with applied voltage is called the voltage coefficient of capacitance (VOC) measured in parts per million. Generally, the VOC of capacitors used on integrated circuits is not zero (50-300 ppm) and hence needs to be nulled. Circuit techniques that employ null methods assume that the variation of VOC with voltage, while not zero, is a linear function of voltage, which is not a valid assumption in integrated circuit capacitors. Furthermore, while these techniques increase precision and resolution of ADC's they consume chip area, and hence increase chip cost. If the VOC of the capacitors is less than a few ppm, one does not need to employ null circuit techniques, thereby reducing circuit complexity and cost.
U.S. Pat. No. 5,108,941 to Paterson et al. discloses a method of making a metal to polysilicon type capacitor having a low VOC as compared to polysilicon type capacitors. In the Paterson et al. method the bottom plate of the capacitor is formed over a field oxide structure, and the multilevel dielectric is deposited thereover. The multilevel dielectric is removed from the capacitor area, and an oxide/nitride dielectric is deposited over the exposed bottom plate and over the multilevel dielectric by way of low pressure chemical vapor deposition ("LPCVD") . A first layer of titanium/tungsten is preferably deposited prior to contact etch, and the contacts to moat and unrelated polysilicon are formed. Metallization is sputtered overall, and the metal and titanium/tungsten are cleared to leave the metallization filling the contact holes, and a capacitor having a titanium/tungsten and metal top plate.
Other disadvantages associated with prior art devices include parasitic capacitance which arises when the intended capacitor and the parasitic capacitor are positioned too close together within the integrated circuit. Conventional designs do not provide for relatively large separation distances between the intended capacitor and the parasitic capacitor because of size restrictions. Moreover, the capacitor is typically connected directly to the polysilicon located on the prior level within the integrated circuit device. Further, conventional capacitor designs typically have non-planar surfaces associated therewith, and as such, the dielectric may not be uniformly deposited over the capacitor area, which may consequently promote voltage breakdown of the capacitor.
In any fabrication process, simplicity is an advantage. Thus, a fabrication method which can achieve the same or better quality product with the same cost of materials while using fewer steps is highly preferred, especially if elimination of fabrication steps reduces labor costs and the need for expensive manufacturing equipment. A new structure built from materials already being used in the fabrication process is preferred since it reduces materials development efforts and the need for expensive manufacturing equipment.
It is also desirable to have flexibility in the processing steps for fabricating integrated circuits. Particularly, it is highly advantageous to have a modular process forming a capacitor, i.e. a process that can be added as an option to an existing digital process with no changes in sequence operations. Employing a silicide metal on polysilicon ("polycide") as contemplated in U.S. Pat. No. 5,108,941 entails siliciding the entire polysilicon layer to achieve the optimum voltage stability. However, siliciding sharply reduces processing flexibility. For example, with a silicide structure heat treatment of the integrated circuit for such purposes as annealing, diffusion, driving in dopants, smoothing interlevel dielectrics and the like, is limited to temperatures below about 850.degree. C. It would be advantageous to be able to use temperatures above 850.degree. C. and to be able to form low VOC capacitors at various stages of integrated circuit fabrication.